Phillip Jones
Email: phjones@iastate.edu
Phone: 515-294-9208
Title(s):
Associate Professor
Office
329 Durham613 Morrill Rd.
Ames, IA 500112100
Information
Education
Ph.D., Computer Engineering, Washington University St. Louis (2008)
M.S., Electrical Engineering, University of Illinois, Urbana-Champaign (2002)
B.S., Electrical Engineering, University of Illinois, Urbana-Champaign (1999)
Research Areas
Core Area(s): Systems and controls, computing and networking systems, embedded systems, system on chip architectures
Department’s Strategic Area(s): Cyber Infrastructure; data, decisions, networks & autonomy
Publications
Google Scholar Profile: https://scholar.google.com/citations?user=XzBeCwIAAAAJ&hl=en
- Qasaimeh, K. Denolf, A. Khodamoradi, M. Blott, J. Lo, L. Halder, K. Vissers, J. Zambreno, and P. H. Jones, “Benchmarking Vision Kernels and Neural Network Inference Accelerators on Embedded Platforms”, Journal of Systems Architecture (JSA), vol. 113, 2021
- Grieve, M. Davies, P. Jones and J. Zambreno, “ARMOR: A Recompilation and Instrumentation-free Monitoring Architecture for Detecting Memory Exploits”, IEEE Transactions on Computers (TC), vol. 67, issue 8, 2018
- Cauwels, J. Zambreno and P. Jones, “HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter”, Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2018.
- Avey, P. Jones and J. Zambreno, “An FPGA-based Hardware Accelerator for Iris Segmentation”, Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2018.
- Zhang, A. Mills, J. Zambreno and P. Jones, “The Design and Integration of a Software Configurable and Parallelized Coprocessor Architecture for LQR Control”, Journal of Parallel and Distributed Computing (JPDC), vol. 106, pp. 121-131, 2017
- Zhang, J. Zambreno and P. Jones, “An Embedded Scalable Linear Model Predictive Hardware-based Controller using ADMM”, Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2017
- Qasaimeh, P. Jones and J. Zambreno, “A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization”, Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2017
- Attia, K. Townsend, P. Jones and J. Zambreno, “A Reconfigurable Architecture for the Detection of Strongly Connected Components”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015.
Departments
Affiliations
Interests
Adaptive computing systemsEmbedded systemsFault tolerant systemsMicroprocessor off-load hardware for application accelerationReal-time systemsReconfigurable Hardware