Homework 2, Q1

Implement single-cycle MIPS processor and debug and verify your implementation on the Quartus simulation platform. You are provided with a sketch program (cpu.v). You are also provied with a number of building blocks, including register file, instruction memory, data memory, ALU, main control unit, and ALU control unit.

Part I.

You can skip this part if you are familiar with Verilog programming.

First do an exercise for Verilog and Quartus simulation. Here is an example program that XORs two bit vectors:

module my_xor (a, b, c);
    input[31:0] a, b;
    output[31:0] c;

    assign c = a ^ b;
endmodule

Save the program as my_xor.v and do its simulation on Quartus. The Quartus software is installed on computers in lab 1331C Coover (a small room inside 1331). If you can work on your own computer with MS Windows, you can download and install free Quartus II Web Edition 4.1 from Altera web site (on the right side of the page). After starting the Quartus program:

  1. Create a project (File => New Project Wizard). Add my_xor.v into the project;
  2. Create a vector waveform file (File => New, then choose "Other Files" and "Vector Waveform File").
  3. Add nodes a, b, and c to the vector waveform file. Save the file.
  4. Compile and simulation (Menu "Processing => Run Compiler & Simulation", or hotkey Ctrl-Shift-K).
  5. Set the values for a and b, re-run the simulation, and see the changes on c. You can set input values for each time period of a and b.

Part II.

 Now complete the single-cycle processor simulation.

  1. Download prelim.zip.
  2. Create a work directory and unzip "prelim.zip".
  3. Start the Quartus program and open a project file named "cpu.qdf" in the directory.
  4. Open cpu.v and complete it. This is the major part of the project.
  5. Important: change the Quartus compiler setting such that (1) functional simulation is chosen ("Setting=>Simulation=>mode"), and (2) smart compilation is turned on ("Setting=>Compiler=>mode").
  6. Simulate and debug your program. A vector waveform file has been provided in the package.

Here are explanations of the some files contained in the package:

  1. cpu.v: The highest level module for the single-cycle implementation. This is the only file you need to work on.
  2. inst_mem.v: Instruction memory module generated by Quartus "MageWizard PlugIn Manager" (from "Tools" menu).
  3. regfile.v: Register file module generated by Quartus "MageWizard PlugIn Manager".
  4. data_mem.v: Register file module generated by Quartus "MageWizard PlugIn Manager".
  5. alu.v: ALU module
  6. alu_control.v: ALU control implementation

Besides, file regfile.mif contains the initial contents of processor registers, data_mem.mif for data memory, and inst_mem.mif for the MIPS program. Initially both registers $16 and $17 contains values 8, and memory addresses 4 and 8 contains 100 and 200, respectively.

The following program reads the contents of address 4 and 8 into $8 and $9, respectively. If the values in $16 and $17 are equal (it is true for this input), the next instruction is skipped. Then the content of $9 is doubled, and stored to memory address 12.

lw $8, 4($0)
lw $9, 8($0)
beq $16, $17, +1
sub $9, $9, $8
add $9, $9, 9$
noop
sw $9, 12($0)

Verify your implementation:

  1. Compare your simulation output with the sample output. They must be consistent.
  2. Check the register file contents in your simulation report. The values for register 8, 9, 16, 17 should be 100, 400, 8, and 8, respectively. Other registers should be zero.
  3. Check the memory contents in your simulation report ("logic memories" in the simulation report window). The values for memory words 1, 2, 3 (address 4, 8, and 12 from the viewpoint of MIPS program) should 100, 200, and 400, respectively.

Submission

Email the following files (my email address is zzhang@iastate.edu):